Messages in this thread | | | Date | Mon, 23 Jul 2018 10:32:58 +0100 | From | Ben Dooks <> | Subject | Re: [PATCH 2/8] clk: tegra: host1x has fractional divider |
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On 2018-07-23 09:50, Peter De Schrijver wrote: > On Fri, Jul 20, 2018 at 02:45:26PM +0100, Ben Dooks wrote: >> The host1x clock according to both tegra2 and tegra3 manuals is >> an 8bit divider with lsb being fractional. This is running into >> an issue where the host1x is being set on a tegra20a system to >> 266.4MHz but ends up at 222MHz instead. >> > > The fact the hw has a fractional divider, does not mean we're allowed > to use > it. Due to the non 50% duty cycle of fractional divided clocks, they > are not > allowed for certain peripherals. Do you have information indicating > this is > ok for the host1x clock?
Only that's what was setup for the systems we're using. We couldn't match the 2.6 working system without these changes.
-- Ben
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