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    SubjectRe: [PATCH v3 05/20] kvm: arm/arm64: Fix stage2_flush_memslot for 4 level page table
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    On 29/06/18 12:15, Suzuki K Poulose wrote:
    > So far we have only supported 3 level page table with fixed IPA of 40bits.
    > Fix stage2_flush_memslot() to accommodate for 4 level tables.
    >
    > Cc: Marc Zyngier <marc.zyngier@arm.com>
    > Acked-by: Christoffer Dall <cdall@kernel.org>
    > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
    > ---
    > virt/kvm/arm/mmu.c | 3 ++-
    > 1 file changed, 2 insertions(+), 1 deletion(-)
    >
    > diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
    > index 1d90d79..061e6b3 100644
    > --- a/virt/kvm/arm/mmu.c
    > +++ b/virt/kvm/arm/mmu.c
    > @@ -379,7 +379,8 @@ static void stage2_flush_memslot(struct kvm *kvm,
    > pgd = kvm->arch.pgd + stage2_pgd_index(addr);
    > do {
    > next = stage2_pgd_addr_end(addr, end);
    > - stage2_flush_puds(kvm, pgd, addr, next);
    > + if (!stage2_pgd_none(*pgd))
    > + stage2_flush_puds(kvm, pgd, addr, next);
    > } while (pgd++, addr = next, addr != end);
    > }
    >
    >

    Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>

    M.
    --
    Jazz is not dead. It just smells funny...

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