Messages in this thread | | | Subject | Re: [PATCH 2/2] i2c: designware: Add support for a bus clock | From | Andy Shevchenko <> | Date | Tue, 17 Jul 2018 15:23:35 +0300 |
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On Tue, 2018-07-17 at 14:07 +0200, Simon Horman wrote: > On Mon, Jul 16, 2018 at 09:59:13AM +0100, Phil Edworthy wrote: > > The Synopsys I2C Controller has a bus clock, but typically SoCs hide > > this away. > > However, on some SoCs you need to explicity enable the bus clock in > > order to > > access the registers. > > Therefore, enable an optional bus clock specified by DT.
> > + /* Optional bus clock */ > > + if (!IS_ERR(dev->busclk)) { > > I suspect that error values stored in dev->busclk, other than > -ENOENT, > should be treated as errors.
While your point sounds valid (don't remember how clk_get() is implemented), NULL is also OK to have.
-- Andy Shevchenko <andriy.shevchenko@linux.intel.com> Intel Finland Oy
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