Messages in this thread | | | Date | Tue, 17 Jul 2018 15:37:50 -0400 (EDT) | From | Alan Stern <> | Subject | Re: [PATCH v2] tools/memory-model: Add extra ordering for locks and remove it for ordinary release/acquire |
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On Tue, 17 Jul 2018, Linus Torvalds wrote:
> On Tue, Jul 17, 2018 at 11:31 AM Paul E. McKenney > <paulmck@linux.vnet.ibm.com> wrote: > > > > The isync provides ordering roughly similar to lwsync, but nowhere near > > as strong as sync, and it is sync that would be needed to cause lock > > acquisition to provide full ordering. > > That's only true when looking at isync in isolation. > > Read the part I quoted. The AIX documentation implies that the > *sequence* of load-compare-conditional branch-isync is a memory > barrier, even if isync on its own is now.
I'm not a huge expert on the PowerPC architecture, but I do have a pretty good understanding of the widely accepted memory model published by the Peter Sewell's group at Cambridge (PPCMEM). According to that model, load-compare-conditional branch-isync is _not_ a full memory barrier.
> So I'm just saying that > > (a) isync-on-lock is supposed to be much cheaper than sync-on-lock > > (b) the AIX documentation at least implies that isync-on-lock (when > used together the the whole locking sequence) is actually a memory > barrier > > Now, admittedly the powerpc barrier instructions are unfathomable > crazy stuff, so who knows. But: > > (a) lwsync is a memory barrier for all the "easy" cases (ie > load->store, load->load, and store->load). > > (b) lwsync is *not* a memory barrier for the store->load case. > > (c) isync *is* (when in that *sequence*) a memory barrier for a > store->load case (and has to be: loads inside a spinlocked region MUST > NOT be done earlier than stores outside of it!).
Why not? Instructions are allowed to migrate _into_ critical sections, just not _out_ of them. So a store preceding the start of a spinlocked region can migrate in and be executed after a load that is inside the region.
Alan Stern
> So a unlock/lock sequence where the unlock is using lwsync, and the > lock is using isync, should in fact be a full memory barrier (which is > the semantics we're looking for). > > So doing performance testing on sync/lwsync (for lock/unlock > respectively) seems the wrong thing to do. Please test the > isync/lwsync case instead. > > Hmm? What am I missing?
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