Messages in this thread | | | Date | Sat, 14 Jul 2018 11:20:51 +0800 | From | kbuild test robot <> | Subject | Re: [PATCH v2 4/4] clk: qcom: Add graphics clock controller driver for SDM845 |
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Hi Amit,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on agross/for-next] [also build test ERROR on v4.18-rc4 next-20180713] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Amit-Nischal/Add-QCOM-graphics-clock-controller-driver-for-SDM845/20180714-080708 base: https://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git for-next config: i386-allmodconfig (attached as .config) compiler: gcc-7 (Debian 7.3.0-16) 7.3.0 reproduce: # save the attached .config to linux build tree make ARCH=i386
All errors (new ones prefixed by >>):
>> drivers/clk/qcom/gpucc-sdm845.c:136:2: error: implicit declaration of function 'F'; did you mean 'FS'? [-Werror=implicit-function-declaration] F(19200000, P_BI_TCXO, 1, 0, 0), ^ FS drivers/clk/qcom/gpucc-sdm845.c:136:2: error: initializer element is not constant drivers/clk/qcom/gpucc-sdm845.c:136:2: note: (near initialization for 'ftbl_gpu_cc_gmu_clk_src[0].freq') drivers/clk/qcom/gpucc-sdm845.c:137:2: error: initializer element is not constant F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), ^ drivers/clk/qcom/gpucc-sdm845.c:137:2: note: (near initialization for 'ftbl_gpu_cc_gmu_clk_src[0].src') drivers/clk/qcom/gpucc-sdm845.c:138:2: error: initializer element is not constant F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0), ^ drivers/clk/qcom/gpucc-sdm845.c:138:2: note: (near initialization for 'ftbl_gpu_cc_gmu_clk_src[0].pre_div') drivers/clk/qcom/gpucc-sdm845.c:139:2: warning: braces around scalar initializer { } ^ drivers/clk/qcom/gpucc-sdm845.c:139:2: note: (near initialization for 'ftbl_gpu_cc_gmu_clk_src[0].m') cc1: some warnings being treated as errors
vim +136 drivers/clk/qcom/gpucc-sdm845.c
134 135 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { > 136 F(19200000, P_BI_TCXO, 1, 0, 0), 137 F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), 138 F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0), 139 { } 140 }; 141
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