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    Subject[PATCH 4.16 34/48] net: phy: broadcom: Fix auxiliary control register reads
    Date
    4.16-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Florian Fainelli <f.fainelli@gmail.com>

    [ Upstream commit 733a969a7ed14fc5786bcc59c1bdda83c7ddb46e ]

    We are currently doing auxiliary control register reads with the shadow
    register value 0b111 (0x7) which incidentally is also the selector value
    that should be present in bits [2:0]. Fix this by using the appropriate
    selector mask which is defined (MII_BCM54XX_AUXCTL_SHDWSEL_MASK).

    This does not have a functional impact yet because we always access the
    MII_BCM54XX_AUXCTL_SHDWSEL_MISC (0x7) register in the current code.
    This might change at some point though.

    Fixes: 5b4e29005123 ("net: phy: broadcom: add bcm54xx_auxctl_read")
    Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
    Signed-off-by: David S. Miller <davem@davemloft.net>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/net/phy/bcm-phy-lib.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    --- a/drivers/net/phy/bcm-phy-lib.c
    +++ b/drivers/net/phy/bcm-phy-lib.c
    @@ -56,7 +56,7 @@ int bcm54xx_auxctl_read(struct phy_devic
    /* The register must be written to both the Shadow Register Select and
    * the Shadow Read Register Selector
    */
    - phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum |
    + phy_write(phydev, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUXCTL_SHDWSEL_MASK |
    regnum << MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT);
    return phy_read(phydev, MII_BCM54XX_AUX_CTL);
    }

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