Messages in this thread | | | Date | Sat, 09 Jun 2018 08:23:51 +0200 | From | Stefan Agner <> | Subject | Re: [PATCH v3 4/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver |
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On 09.06.2018 07:52, Boris Brezillon wrote: > On Fri, 08 Jun 2018 23:51:01 +0200 > Stefan Agner <stefan@agner.ch> wrote: > > >> > >> > void tegra_nand_controller_reset(struct tegra_nand_controller *ctrl) >> > { >> > int err; >> > >> > disable_irq(ctrl->irq); >> > >> > err = reset_control_reset(ctrl->rst); >> > if (err) { >> > dev_err(ctrl->dev, "Failed to reset HW: %d\n", err); >> > msleep(HW_TIMEOUT); >> > } >> > >> > writel_relaxed(NAND_CMD_STATUS, ctrl->regs + HWSTATUS_CMD); >> > writel_relaxed(HWSTATUS_MASK, ctrl->regs + HWSTATUS_MASK); >> > writel_relaxed(INT_MASK, ctrl->regs + ISR); >> >> If we do a controller reset, there is much more state than that which >> needs to be restored. A lot of it is not readily available currently >> (timing, ECC settings...) > > This is actually a good test to detect what is not properly initialized > by the driver. Timings should be configured correctly through > ->setup_data_interface(). ECC engine should be disabled by default and > only enabled when ->{read,write}_page() is called. >
Is setup_data_interface guaranteed to be called after a failed ->exec_op()/{read,write}_page()?
>> >> That seems a lot of work for a code path I do not intend to ever use :-) >> > > Not so sure it's a lot of work. If ECC and timing settings are the > only thing you need to initialize then it should work just fine. > Try with a controller reset and you'll know if you miss something ;-).
Currently the setting gets written directly to the registers. Only the enable flag is set in the HW ECC {read,write}_page() functions. So I will have to store the complete register in the chip structure and write them on every {read,write}_page()?
-- Stefan
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