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    Subject[PATCH 4.16 23/47] drm/amd/powerplay: Fix enum mismatch
    Date
    4.16-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Matthias Kaehlcke <mka@chromium.org>

    commit 42b5122e828a6ccd9952ad3116343dc032d33efe upstream.

    In several locations the driver uses AMD_CG_STATE_UNGATE (type enum
    amd_clockgating_state) instead of AMD_PG_STATE_UNGATE (type enum
    amd_powergating_stat) and vice versa. Both constants have the same
    value, so this doesn't cause any problems, but we still want to pass
    the correct type.

    Fixing the mismatch resolves multiple warnings like this when building
    with clang:

    drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_clockpowergating.c:169:7:
    error: implicit conversion from enumeration type 'enum
    amd_powergating_state' to different enumeration type 'enum
    amd_clockgating_state' [-Werror,-Wenum-conversion]
    AMD_PG_STATE_UNGATE);

    Reviewed-by: Guenter Roeck <groeck@chromium.org>
    Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c | 8 ++++----
    drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c | 2 +-
    2 files changed, 5 insertions(+), 5 deletions(-)

    --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
    +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
    @@ -166,10 +166,10 @@ void cz_dpm_powergate_uvd(struct pp_hwmg
    cz_dpm_powerup_uvd(hwmgr);
    cgs_set_clockgating_state(hwmgr->device,
    AMD_IP_BLOCK_TYPE_UVD,
    - AMD_PG_STATE_UNGATE);
    + AMD_CG_STATE_UNGATE);
    cgs_set_powergating_state(hwmgr->device,
    AMD_IP_BLOCK_TYPE_UVD,
    - AMD_CG_STATE_UNGATE);
    + AMD_PG_STATE_UNGATE);
    cz_dpm_update_uvd_dpm(hwmgr, false);
    }

    @@ -197,11 +197,11 @@ void cz_dpm_powergate_vce(struct pp_hwmg
    cgs_set_clockgating_state(
    hwmgr->device,
    AMD_IP_BLOCK_TYPE_VCE,
    - AMD_PG_STATE_UNGATE);
    + AMD_CG_STATE_UNGATE);
    cgs_set_powergating_state(
    hwmgr->device,
    AMD_IP_BLOCK_TYPE_VCE,
    - AMD_CG_STATE_UNGATE);
    + AMD_PG_STATE_UNGATE);
    cz_dpm_update_vce_dpm(hwmgr);
    cz_enable_disable_vce_dpm(hwmgr, true);
    }
    --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
    +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
    @@ -162,7 +162,7 @@ void smu7_powergate_uvd(struct pp_hwmgr
    AMD_CG_STATE_UNGATE);
    cgs_set_powergating_state(hwmgr->device,
    AMD_IP_BLOCK_TYPE_UVD,
    - AMD_CG_STATE_UNGATE);
    + AMD_PG_STATE_UNGATE);
    smu7_update_uvd_dpm(hwmgr, false);
    }


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