Messages in this thread | | | Date | Mon, 25 Jun 2018 10:19:20 +0200 | From | Andrea Parri <> | Subject | Re: [PATCH 2/2] tools/memory-model: Add write ordering by release-acquire and by locks |
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On Fri, Jun 22, 2018 at 07:30:08PM +0100, Will Deacon wrote: > > > I think the second example would preclude us using LDAPR for load-acquire,
> I don't think it's a moot point. We want new architectures to implement > acquire/release efficiently, and it's not unlikely that they will have > acquire loads that are similar in semantics to LDAPR. This patch prevents > them from doing so,
By this same argument, you should not be a "big fan" of rfi-rel-acq in ppo ;) consider, e.g., the two litmus tests below: what am I missing?
Andrea
C MP+fencewmbonceonce+pooncerelease-rfireleaseacquire-poacquireonce
{}
P0(int *x, int *y) { WRITE_ONCE(*x, 1); smp_wmb(); WRITE_ONCE(*y, 1); }
P1(int *x, int *y, int *z) { r0 = READ_ONCE(*y); smp_store_release(z, 1); r1 = smp_load_acquire(z); r2 = READ_ONCE(*x); }
exists (1:r0=1 /\ 1:r1=1 /\ 1:r2=0)
AArch64 MP+dmb.st+popl-rfilq-poqp "DMB.STdWW Rfe PodRWPL RfiLQ PodRRQP Fre" Generator=diyone7 (version 7.49+02(dev)) Prefetch=0:x=F,0:y=W,1:y=F,1:x=T Com=Rf Fr Orig=DMB.STdWW Rfe PodRWPL RfiLQ PodRRQP Fre { 0:X1=x; 0:X3=y; 1:X1=y; 1:X3=z; 1:X6=x; } P0 | P1 ; MOV W0,#1 | LDR W0,[X1] ; STR W0,[X1] | MOV W2,#1 ; DMB ST | STLR W2,[X3] ; MOV W2,#1 | LDAPR W4,[X3] ; STR W2,[X3] | LDR W5,[X6] ; exists (1:X0=1 /\ 1:X4=1 /\ 1:X5=0)
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