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    Subject[PATCH 4.14 389/496] iommu/mediatek: Fix protect memory setting
    Date
    4.14-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Yong Wu <yong.wu@mediatek.com>

    [ Upstream commit 70ca608b2ec6dafa6bb1c2b0691852fc78f8f717 ]

    In MediaTek's IOMMU design, When a iommu translation fault occurs
    (HW can NOT translate the destination address to a valid physical
    address), the IOMMU HW output the dirty data into a special memory
    to avoid corrupting the main memory, this is called "protect memory".
    the register(0x114) for protect memory is a little different between
    mt8173 and mt2712.

    In the mt8173, bit[30:6] in the register represents [31:7] of the
    physical address. In the 4GB mode, the register bit[31] should be 1.
    While in the mt2712, the bits don't shift. bit[31:7] in the register
    represents [31:7] in the physical address, and bit[1:0] in the
    register represents bit[33:32] of the physical address if it has.

    Fixes: e6dec9230862 ("iommu/mediatek: Add mt2712 IOMMU support")
    Reported-by: Honghui Zhang <honghui.zhang@mediatek.com>
    Signed-off-by: Yong Wu <yong.wu@mediatek.com>
    Signed-off-by: Joerg Roedel <jroedel@suse.de>
    Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/iommu/mtk_iommu.c | 15 ++++++++++-----
    drivers/iommu/mtk_iommu.h | 1 +
    2 files changed, 11 insertions(+), 5 deletions(-)

    --- a/drivers/iommu/mtk_iommu.c
    +++ b/drivers/iommu/mtk_iommu.c
    @@ -60,7 +60,7 @@
    (((prot) & 0x3) << F_MMU_TF_PROTECT_SEL_SHIFT(data))

    #define REG_MMU_IVRP_PADDR 0x114
    -#define F_MMU_IVRP_PA_SET(pa, ext) (((pa) >> 1) | ((!!(ext)) << 31))
    +
    #define REG_MMU_VLD_PA_RNG 0x118
    #define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA))

    @@ -532,8 +532,13 @@ static int mtk_iommu_hw_init(const struc
    F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
    writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);

    - writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base, data->enable_4GB),
    - data->base + REG_MMU_IVRP_PADDR);
    + if (data->m4u_plat == M4U_MT8173)
    + regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
    + else
    + regval = lower_32_bits(data->protect_base) |
    + upper_32_bits(data->protect_base);
    + writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
    +
    if (data->enable_4GB && data->m4u_plat != M4U_MT8173) {
    /*
    * If 4GB mode is enabled, the validate PA range is from
    @@ -688,6 +693,7 @@ static int __maybe_unused mtk_iommu_susp
    reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
    reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0);
    reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
    + reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR);
    clk_disable_unprepare(data->bclk);
    return 0;
    }
    @@ -710,8 +716,7 @@ static int __maybe_unused mtk_iommu_resu
    writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
    writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
    writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
    - writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base, data->enable_4GB),
    - base + REG_MMU_IVRP_PADDR);
    + writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR);
    if (data->m4u_dom)
    writel(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0],
    base + REG_MMU_PT_BASE_ADDR);
    --- a/drivers/iommu/mtk_iommu.h
    +++ b/drivers/iommu/mtk_iommu.h
    @@ -32,6 +32,7 @@ struct mtk_iommu_suspend_reg {
    u32 ctrl_reg;
    u32 int_control0;
    u32 int_main_control;
    + u32 ivrp_paddr;
    };

    enum mtk_iommu_plat {

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