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    Subject[PATCH 4.14 485/496] drm: rcar-du: lvds: Fix LVDS startup on R-Car Gen3
    Date
    4.14-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

    [ Upstream commit 796ceb9269626afaed3b4955c40d2c3d7a8c5d01 ]

    According to the latest revisions of the R-Car Gen3 manual, the LVDS mode
    must be set before the LVDS I/O pins are enabled, not after -- fix the
    Gen3 LVDS startup sequence accordingly.

    Fixes: e947eccbeba4 ("drm: rcar-du: Add support for LVDS mode selection")
    Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
    Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
    [Updated comment in rcar_du_lvdsenc_start_gen3()]
    [Moved Gen2 startup comment update to separate commit]
    [Fixed =| typo]
    Tested-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
    Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
    Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c | 7 +++++--
    1 file changed, 5 insertions(+), 2 deletions(-)

    --- a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
    +++ b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
    @@ -95,7 +95,7 @@ static void rcar_du_lvdsenc_start_gen3(s
    u32 lvdcr0;
    u32 pllcr;

    - /* PLL clock configuration */
    + /* Set the PLL clock configuration and LVDS mode. */
    if (freq < 42000)
    pllcr = LVDPLLCR_PLLDIVCNT_42M;
    else if (freq < 85000)
    @@ -107,6 +107,9 @@ static void rcar_du_lvdsenc_start_gen3(s

    rcar_lvds_write(lvds, LVDPLLCR, pllcr);

    + lvdcr0 = lvds->mode << LVDCR0_LVMD_SHIFT;
    + rcar_lvds_write(lvds, LVDCR0, lvdcr0);
    +
    /* Turn all the channels on. */
    rcar_lvds_write(lvds, LVDCR1,
    LVDCR1_CHSTBY_GEN3(3) | LVDCR1_CHSTBY_GEN3(2) |
    @@ -117,7 +120,7 @@ static void rcar_du_lvdsenc_start_gen3(s
    * Turn the PLL on, set it to LVDS normal mode, wait for the startup
    * delay and turn the output on.
    */
    - lvdcr0 = (lvds->mode << LVDCR0_LVMD_SHIFT) | LVDCR0_PLLON;
    + lvdcr0 |= LVDCR0_PLLON;
    rcar_lvds_write(lvds, LVDCR0, lvdcr0);

    lvdcr0 |= LVDCR0_PWD;

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