Messages in this thread Patch in this message | | | From | David Wang <> | Subject | [PATCH 3/3] x86/Centaur: Report correct CPU/cache topology | Date | Thu, 3 May 2018 10:32:46 +0800 |
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Centaur CPUs enumerate the cache topology in the same way as Intel CPUs, but the function is unused so for. The Centaur init code also missies to initialize x86_info::max_cores, so the CPU topology can't be described correctly.
Initialize x86_info::max_cores and invoke init_intel_cacheinfo() to make CPU and cache topology information available and correct.
Signed-off-by: David Wang <davidwang@zhaoxin.com> --- arch/x86/kernel/cpu/centaur.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c index 80d5110..c265494 100644 --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -160,6 +160,11 @@ static void init_centaur(struct cpuinfo_x86 *c) clear_cpu_cap(c, 0*32+31); #endif early_init_centaur(c); + init_intel_cacheinfo(c); + c->x86_max_cores = detect_num_cpu_cores(c); +#ifdef CONFIG_X86_32 + detect_ht(c); +#endif if (c->cpuid_level > 9) { unsigned int eax = cpuid_eax(10); -- 1.9.1
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