Messages in this thread | | | Date | Fri, 18 May 2018 17:26:51 +0200 | From | Maxime Ripard <> | Subject | Re: [PATCH v2 12/26] drm/sun4i: Add support for multiple DW HDMI PHY clock parents |
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On Fri, May 18, 2018 at 04:46:41PM +0200, Jernej Škrabec wrote: > > And this is a bit sloppy, since if phy_clk_num == 3, you won't try to > > lookup pll-2 either. > > It is highly unlikely this will be higher than 2, at least for this HDMI PHY, > since it has only 1 bit reserved for parent selection. But since I have to fix > it, I'll add ">= 2"
If we're only going to have two parents at most, ever, why don't we had just a single other boolean. This would be less intrusive, and we wouldn't have to check for those corner cases.
> BTW, I'll resend fixed version of this patch for my R40 HDMI series, since > there is nothing to hold it back, unlike for this.
Awesome, thanks! Maxime
-- Maxime Ripard, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com [unhandled content-type:application/pgp-signature] | |