Messages in this thread Patch in this message |  | | From | Taniya Das <> | Subject | [PATCH v2 2/3] clk: qcom: gdsc: Add support to poll for higher timeout value | Date | Mon, 9 Apr 2018 14:11:45 +0530 |
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From: Amit Nischal <anischal@codeaurora.org>
For some gdscs, it might take longer time up to 500us for updating their status. Update the timeout value for all GDSC polling status.
Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> --- drivers/clk/qcom/gdsc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 266fefa..cb61c15 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -41,7 +41,7 @@ #define RETAIN_MEM BIT(14) #define RETAIN_PERIPH BIT(13)
-#define TIMEOUT_US 100 +#define TIMEOUT_US 500
#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
-- Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
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