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    Subject[PATCH AUTOSEL for 4.9 278/293] arm64: spinlock: Fix theoretical trylock() A-B-A with LSE atomics
    Date
    From: Will Deacon <will.deacon@arm.com>

    [ Upstream commit 202fb4ef81e3ec765c23bd1e6746a5c25b797d0e ]

    If the spinlock "next" ticket wraps around between the initial LDR
    and the cmpxchg in the LSE version of spin_trylock, then we can erroneously
    think that we have successfuly acquired the lock because we only check
    whether the next ticket return by the cmpxchg is equal to the owner ticket
    in our updated lock word.

    This patch fixes the issue by performing a full 32-bit check of the lock
    word when trying to determine whether or not the CASA instruction updated
    memory.

    Reported-by: Catalin Marinas <catalin.marinas@arm.com>
    Signed-off-by: Will Deacon <will.deacon@arm.com>
    Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
    Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
    ---
    arch/arm64/include/asm/spinlock.h | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    diff --git a/arch/arm64/include/asm/spinlock.h b/arch/arm64/include/asm/spinlock.h
    index cae331d553f8..a9d2dd03c977 100644
    --- a/arch/arm64/include/asm/spinlock.h
    +++ b/arch/arm64/include/asm/spinlock.h
    @@ -141,8 +141,8 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock)
    " cbnz %w1, 1f\n"
    " add %w1, %w0, %3\n"
    " casa %w0, %w1, %2\n"
    - " and %w1, %w1, #0xffff\n"
    - " eor %w1, %w1, %w0, lsr #16\n"
    + " sub %w1, %w1, %3\n"
    + " eor %w1, %w1, %w0\n"
    "1:")
    : "=&r" (lockval), "=&r" (tmp), "+Q" (*lock)
    : "I" (1 << TICKET_SHIFT)
    --
    2.15.1
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