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SubjectRe: [PATCH net-next v2 2/2] dt: bindings: add new dt entries for brcmfmac
On 5 April 2018 at 15:10, Kalle Valo <> wrote:
> Ulf Hansson <> writes:
>> On 20 March 2018 at 10:55, Kalle Valo <> wrote:
>>> Arend van Spriel <> writes:
>>>>>> If I get it right, you mean something like this:
>>>>>> mmc3: mmc@1c12000 {
>>>>>> ...
>>>>>> broken-sg-support;
>>>>>> sd-head-align = 4;
>>>>>> sd-sgentry-align = 512;
>>>>>> brcmf: wifi@1 {
>>>>>> ...
>>>>>> };
>>>>>> };
>>>>>> Where dt: bindings documentation for these entries should reside?
>>>>>> In generic MMC bindings? Well, this is the very special case and
>>>>>> mmc-linux maintainer will unlikely to accept these changes.
>>>>>> Also, extra kernel code modification might be required. It could make
>>>>>> quite trivial change much more complex.
>>>>> If the MMC maintainers are not copied on this patch series, it will
>>>>> likely be hard for them to identify this patch series and chime in...
>>>> The main question is whether this is indeed a "very special case" as
>>>> Alexey claims it to be or that it is likely to be applicable to other
>>>> device and host combinations as you are suggesting.
>>>> If these properties are imposed by the host or host controller it
>>>> would make sense to have these in the mmc bindings.
>>> BTW, last year we were discussing something similar (I mean related to
>>> alignment requirements) with ath10k SDIO patches and at the time the
>>> patch submitter was proposing to have a bounce buffer in ath10k to
>>> workaround that. I don't remember the details anymore, they are on the
>>> ath10k mailing list archive if anyone is curious to know, but I would
>>> not be surprised if they are similar as here. So there might be a need
>>> to solve this in a generic way (but not sure of course as I haven't
>>> checked the details).
>> I re-call something about these as well, here are the patches. Perhaps
>> I should pick some of them up...
> Actually I was talking about a different patch, found it now:
> ath10k_sdio: DMA bounce buffers for read write

Ah, yes. This is about buffer alignment, particularly when using DMA.

Normally there should be no constraint on the alignment, if the
mmc/sdio controller driver would implement a fallback mechanism from
DMA to PIO mode, in case the buffer can't be used for DMA.

However, I know about cases where simply PIO doesn't work because of
broken HW and in many cases the mmc drivers don't implement the
fallback to PIO even if they could.

Moreover, it seems reasonable to anyway have a way for mmc driver to
inform upper layers about DMA buffer alignment constraints, as to be
able to use DMA as long as possible.


Kind regards

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