Messages in this thread Patch in this message | | | From | Dmitry Osipenko <> | Subject | [PATCH v1 3/4] clk: tegra20: Set correct parents for CDEV1/2 clocks | Date | Fri, 27 Apr 2018 02:58:17 +0300 |
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Parents of CDEV1/2 clocks are determined by muxing of the corresponding pins. Pinctrl driver now provides the CDEV1/2 clock muxes and hence CDEV1/2 clocks could have correct parents. Set CDEV1/2 parents to the corresponding muxes to fix the parents.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- drivers/clk/tegra/clk-tegra20.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 16cf4108f2ff..7e8b6de86d89 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -844,14 +844,12 @@ static void __init tegra20_periph_clk_init(void) CLK_DIVIDER_POWER_OF_TWO, NULL); /* cdev1 */ - clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, 0, 26000000); - clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0, + clk = tegra_clk_register_periph_gate("cdev1", "cdev1_mux", 0, clk_base, 0, 94, periph_clk_enb_refcnt); clks[TEGRA20_CLK_CDEV1] = clk; /* cdev2 */ - clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, 0, 26000000); - clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0, + clk = tegra_clk_register_periph_gate("cdev2", "cdev2_mux", 0, clk_base, 0, 93, periph_clk_enb_refcnt); clks[TEGRA20_CLK_CDEV2] = clk; -- 2.17.0
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