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SubjectRe: [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma
On Mon, 2 Apr 2018 22:20:20 +0200
Boris Brezillon <> wrote:

> >
> > > And
> > > which DDR slave is the target? 7, 8, 9 or 10? More than one?
> >
> > This, I don't know. I guess all of them can be used.
> Looks like I was wrong. According to "Table 15-3. SAMA5D3 Master to
> Slave Access", LCDC port 0 can only access DDR port 2 and LCDC port 1
> can only access DDR port 3.
> Can you try to write 0x3 to 0xFFFFECCC and 0x30 to 0xFFFFECD4?

Oh, one more thing. Changing the priority won't necessarily solve your
problem because of that:

If more than one master requests the slave bus, regardless of the
respective masters priorities, no master will be granted
the slave bus for two consecutive runs. A master can only get
back-to-back grants so long as it is the only requesting

To solve that, you'll have to play with MATRIX_MCFGy.ULBT (make sure
DMAC0 and DMAC1 have a small enough ULBT that is not 0) or
MATRIX_SCFGx.SLOT_CYCLE (that one is probably harder to get right
since it's expressed in AHB clock cycles).

Boris Brezillon, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering

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