Messages in this thread | | | From | Fabio Estevam <> | Date | Thu, 19 Apr 2018 19:15:26 -0300 | Subject | Re: [PATCH] serial: imx: fix cached UCR2 read on software reset |
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On Mon, Apr 16, 2018 at 12:35 PM, Stefan Agner <stefan@agner.ch> wrote: > To reset the UART the SRST needs be cleared (low active). According > to the documentation the bit will remain active for 4 module clocks > until it is cleared (set to 1). > > Hence the real register need to be read in case the cached register > indcates that the SRST bit is zero.
s/indcates/indicates
> This bug lead to wrong baudrate because the baud rate register got > restored before reset completed in imx_flush_buffer. > > Fixes: 3a0ab62f43de ("serial: imx: implement shadow registers for UCRx and UFCR") > Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
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