[lkml]   [2018]   [Apr]   [18]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
SubjectRe: [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SDM845
Hi Amit,

On 4/18/2018 6:33 PM, Amit Nischal wrote:
>>> +       /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */
>>> +       regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
>>> +       regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
>> I think we'll have to throw in the pipe clk branch stuff in here too?
>> And then drop the pipe clks from the driver?
> All the USB pipe clocks would be taken care. The PCIE pipe branch
> clocks would have to be explicitly disabled so as to retain the
> memory logic. Otherwise, it would lead to memory corruption in case
> the external source is directly disabled without disabling the branch clock.

PHY driver is same for both USB and PCIE and both PHYs use pipe_clk.
If there is indeed some limitation and pipe_clk cant be left enabled
always then I will suggest to not change pipe_clk handling for USB as well.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

 \ /
  Last update: 2018-04-18 18:39    [W:0.045 / U:0.092 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site