Messages in this thread | | | From | Stephen Boyd <> | Subject | Re: [PATCH] clk: mediatek: correct the clocks for MT2701 HDMI PHY module | Date | Mon, 16 Apr 2018 09:34:55 -0700 |
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Quoting Ryder Lee (2018-04-15 19:31:58) > The hdmitx_dig_cts clock signal is not a child of clk26m, > and the actual output of the PLL block is derived from > the tvdpll via a configurable PLL post-divider. > > It is used as the PLL reference input to the HDMI PHY module. > > Signed-off-by: Chunhui Dai <chunhui.dai@mediatek.com> > Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Any sort of Fixes: tag here?
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