Messages in this thread Patch in this message | | | From | Jacopo Mondi <> | Subject | [PATCH v2 1/4] arm64: dts: renesas: r8a77970: add VSPD support | Date | Tue, 10 Apr 2018 12:54:03 +0200 |
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From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Describe VSPD0 in the R8A77970 device tree; it will be used by DU in the next patch...
Based on the original (and large) patch by Daisuke Matsushita <daisuke.matsushita.ns@hitachi.com>.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
v1 -> v2: - Extend the memory region to include V6_CLUTn_TBL* registers. --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 97c27ef..a3ef3bd 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -625,6 +625,16 @@ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 603>; }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x8000>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 623>; + renesas,fcp = <&fcpvd0>; + }; }; timer { -- 2.7.4
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