Messages in this thread | | | Date | Fri, 9 Mar 2018 13:48:13 +0000 | From | Will Deacon <> | Subject | Re: [PATCH v7] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC |
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On Wed, Mar 07, 2018 at 09:00:08AM -0600, Shanker Donthineni wrote: > The DCache clean & ICache invalidation requirements for instructions > to be data coherence are discoverable through new fields in CTR_EL0. > The following two control bits DIC and IDC were defined for this > purpose. No need to perform point of unification cache maintenance > operations from software on systems where CPU caches are transparent. > > This patch optimize the three functions __flush_cache_user_range(), > clean_dcache_area_pou() and invalidate_icache_range() if the hardware > reports CTR_EL0.IDC and/or CTR_EL0.IDC. Basically it skips the two > instructions 'DC CVAU' and 'IC IVAU', and the associated loop logic > in order to avoid the unnecessary overhead.
Cheers, I've queued this for 4.17.
Will
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