lkml.org 
[lkml]   [2018]   [Mar]   [5]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
SubjectRe: [PATCH] ARM: dts: rockchip: Add dp83867 CLK_OUT muxing
Date
Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz:
> The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz.
> Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.
>
> Signed-off-by: Daniel Schultz <d.schultz@phytec.de>

applied for 4.17


Thanks
Heiko

\
 
 \ /
  Last update: 2018-03-05 21:26    [W:0.070 / U:0.304 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site