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    Subject[PATCH 4.15 046/105] media: tegra-cec: reset rx_buf_cnt when start bit detected
    Date
    4.15-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Hans Verkuil <hverkuil@xs4all.nl>

    commit e113d65ae417ae6d9be229649b81d404c47ade79 upstream.

    If a start bit is detected, then reset the receive buffer counter to 0.

    This ensures that no stale data is in the buffer if a message is
    broken off midstream due to e.g. a Low Drive condition and then
    retransmitted.

    The only Rx interrupts we need to listen to are RX_REGISTER_FULL (i.e.
    a valid byte was received) and RX_START_BIT_DETECTED (i.e. a new
    message starts and we need to reset the counter).

    Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
    Cc: <stable@vger.kernel.org> # for v4.15 and up
    Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/media/platform/tegra-cec/tegra_cec.c | 17 +++++++----------
    1 file changed, 7 insertions(+), 10 deletions(-)

    --- a/drivers/media/platform/tegra-cec/tegra_cec.c
    +++ b/drivers/media/platform/tegra-cec/tegra_cec.c
    @@ -172,16 +172,13 @@ static irqreturn_t tegra_cec_irq_handler
    }
    }

    - if (status & (TEGRA_CEC_INT_STAT_RX_REGISTER_OVERRUN |
    - TEGRA_CEC_INT_STAT_RX_BUS_ANOMALY_DETECTED |
    - TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED |
    - TEGRA_CEC_INT_STAT_RX_BUS_ERROR_DETECTED)) {
    + if (status & TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED) {
    cec_write(cec, TEGRA_CEC_INT_STAT,
    - (TEGRA_CEC_INT_STAT_RX_REGISTER_OVERRUN |
    - TEGRA_CEC_INT_STAT_RX_BUS_ANOMALY_DETECTED |
    - TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED |
    - TEGRA_CEC_INT_STAT_RX_BUS_ERROR_DETECTED));
    - } else if (status & TEGRA_CEC_INT_STAT_RX_REGISTER_FULL) {
    + TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED);
    + cec->rx_done = false;
    + cec->rx_buf_cnt = 0;
    + }
    + if (status & TEGRA_CEC_INT_STAT_RX_REGISTER_FULL) {
    u32 v;

    cec_write(cec, TEGRA_CEC_INT_STAT,
    @@ -255,7 +252,7 @@ static int tegra_cec_adap_enable(struct
    TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED |
    TEGRA_CEC_INT_MASK_TX_FRAME_TRANSMITTED |
    TEGRA_CEC_INT_MASK_RX_REGISTER_FULL |
    - TEGRA_CEC_INT_MASK_RX_REGISTER_OVERRUN);
    + TEGRA_CEC_INT_MASK_RX_START_BIT_DETECTED);

    cec_write(cec, TEGRA_CEC_HW_CONTROL, TEGRA_CEC_HWCTRL_TX_RX_MODE);
    return 0;

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