Messages in this thread |  | | Date | Fri, 23 Mar 2018 22:22:30 +0100 | From | Alexandre Belloni <> | Subject | Re: [PATCH net-next 6/8] MIPS: mscc: Add switch to ocelot |
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On 23/03/2018 at 14:17:48 -0700, Florian Fainelli wrote: > On 03/23/2018 01:11 PM, Alexandre Belloni wrote: > > + > > + phy0: ethernet-phy@0 { > > + reg = <0>; > > + }; > > + phy1: ethernet-phy@1 { > > + reg = <1>; > > + }; > > + phy2: ethernet-phy@2 { > > + reg = <2>; > > + }; > > + phy3: ethernet-phy@3 { > > + reg = <3>; > > + }; > > These PHYs should be defined at the board DTS level.
Those are internal PHYs, present on the SoC, I doubt anyone will have anything different while using the same SoC.
-- Alexandre Belloni, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com
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