Messages in this thread | | | Date | Tue, 20 Mar 2018 10:03:11 +0100 (CET) | From | Thomas Gleixner <> | Subject | Re: [PATCH] x86/ioapic: don't use unstable TSC to detect timer IRQ |
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On Tue, 20 Mar 2018, Liu, Changcheng wrote:
> On 09:49 Tue 20 Mar, Peter Zijlstra wrote: > > On Tue, Mar 20, 2018 at 04:42:55PM +0800, Liu, Changcheng wrote: > > > In rare case, the TSC is every unstable or can't sync with > > > real time hardware clock. > > > > However did you manage that? Please provide _FAR_ more details. > [Changcheng] TSC is simulated and HPET is hardware implemented. > TSC can't sync with HPET. When running linux, the TSC grows too > fast and HPET can't trigger periodic timer interrupt in time which > is used to update jiffies.
Why on earth is that system claiming it has a TSC at all? That's just broken.
Thanks,
tglx
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