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    Subject[PATCH AUTOSEL for 4.9 236/281] coresight: tmc: Configure DMA mask appropriately
    Date
    From: Robin Murphy <robin.murphy@arm.com>

    [ Upstream commit a3959c50b02f57df4c4e4f14f632220f1c0b1f79 ]

    Before making any DMA API calls, the ETR driver should really be setting
    its masks to ensure that DMA is possible. Especially since it can
    address more than the 32-bit default mask set by the AMBA bus code.

    Signed-off-by: Robin Murphy <robin.murphy@arm.com>
    Tested-by: Suzuki K Poulose <suzuki.poulose@arm.com>
    Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
    ---
    drivers/hwtracing/coresight/coresight-tmc.c | 7 +++++++
    1 file changed, 7 insertions(+)

    diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
    index d8517d2a968c..864488793f09 100644
    --- a/drivers/hwtracing/coresight/coresight-tmc.c
    +++ b/drivers/hwtracing/coresight/coresight-tmc.c
    @@ -362,6 +362,13 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
    desc.type = CORESIGHT_DEV_TYPE_SINK;
    desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
    desc.ops = &tmc_etr_cs_ops;
    + /*
    + * ETR configuration uses a 40-bit AXI master in place of
    + * the embedded SRAM of ETB/ETF.
    + */
    + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
    + if (ret)
    + goto out;
    } else {
    desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
    desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
    --
    2.14.1
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