| From | Sasha Levin <> | Subject | [PATCH AUTOSEL for 4.15 034/124] clk: sunxi-ng: a83t: Add M divider to TCON1 clock | Date | Mon, 19 Mar 2018 15:47:34 +0000 |
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From: Jernej Škrabec <jernej.skrabec@siol.net>
[ Upstream commit 7dbc7f5f4904cfddc199af171ea095490a434f15 ]
TCON1 also has M divider, contrary to TCON0. And the mux is only 2 bits wide, instead of 3.
Fixes: 05359be1176b ("clk: sunxi-ng: Add driver for A83T CCU") Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> [wens@csie.org: Add description about mux width difference] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> --- drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c index 5cedcd0d8be8..aeafa7a4fff5 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c @@ -493,8 +493,8 @@ static SUNXI_CCU_MUX_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents, 0x118, 24, 3, BIT(31), CLK_SET_RATE_PARENT); static const char * const tcon1_parents[] = { "pll-video1" }; -static SUNXI_CCU_MUX_WITH_GATE(tcon1_clk, "tcon1", tcon1_parents, - 0x11c, 24, 3, BIT(31), CLK_SET_RATE_PARENT); +static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_clk, "tcon1", tcon1_parents, + 0x11c, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x130, BIT(16), 0); -- 2.14.1 |