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    Subject[PATCH 4.4 015/134] drivers: net: xgene: Fix hardware checksum setting
    Date
    4.4-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Quan Nguyen <qnguyen@apm.com>


    [ Upstream commit e026e700d940a1ea3d3bc84d92ac668b1f015462 ]

    This patch fixes the hardware checksum settings by properly program
    the classifier. Otherwise, packet may be received with checksum error
    on X-Gene1 SoC.

    Signed-off-by: Quan Nguyen <qnguyen@apm.com>
    Signed-off-by: Iyappan Subramanian <isubramanian@apm.com>
    Signed-off-by: David S. Miller <davem@davemloft.net>
    Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/net/ethernet/apm/xgene/xgene_enet_hw.c | 1 +
    drivers/net/ethernet/apm/xgene/xgene_enet_hw.h | 1 +
    2 files changed, 2 insertions(+)

    --- a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.c
    +++ b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.c
    @@ -604,6 +604,7 @@ static void xgene_enet_cle_bypass(struct
    xgene_enet_rd_csr(pdata, CLE_BYPASS_REG0_0_ADDR, &cb);
    cb |= CFG_CLE_BYPASS_EN0;
    CFG_CLE_IP_PROTOCOL0_SET(&cb, 3);
    + CFG_CLE_IP_HDR_LEN_SET(&cb, 0);
    xgene_enet_wr_csr(pdata, CLE_BYPASS_REG0_0_ADDR, cb);

    xgene_enet_rd_csr(pdata, CLE_BYPASS_REG1_0_ADDR, &cb);
    --- a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h
    +++ b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h
    @@ -147,6 +147,7 @@ enum xgene_enet_rm {
    #define CFG_RXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 26, 3)

    #define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2)
    +#define CFG_CLE_IP_HDR_LEN_SET(dst, val) xgene_set_bits(dst, val, 8, 5)
    #define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12)
    #define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4)
    #define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2)

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