lkml.org 
[lkml]   [2018]   [Mar]   [19]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
SubjectRe: [PATCH] clk: mvebu: cp110: Fix clock tree representation
Date
Quoting Gregory CLEMENT (2018-03-13 04:32:47)
> Hi,
>
> On mer., févr. 28 2018, Gregory CLEMENT <gregory.clement@bootlin.com> wrote:
>
> > Thanks to new documentation, we have a better view of the clock tree.
> > There were few mistakes in the first version of this driver, the main one
> > being the parental link between the clocks. Actually the tree is more
> > flat that we though. Most of the IP blocks require two clocks: one for
> > the IP itself and one for accessing the registers, and unlike what we
> > wrote there is no link between these two clocks.
> >
> > The other mistakes were about the name of the clocks: the root clock is
> > not the Audio PLL but the PLL0, and what we called the EIP clock is named
> > the x2 Core clock and is used by other IP block than the EIP ones.
>
> Do you have any feedback on this patch?
>
> I would like to have time to address them if you have any remark.
>
> Else do you want a Pull Request or could you apply it directly?
>
> The only other patch around the mvebu clocks was set a few days ago [1]
> and seems to be eventually a fix patch. That means that there would be
> only one patch in the Pull Request for 4.17, but I can do it if you
> prefer.
>

Please don't send single patch PRs. I'll pick this up. Thanks.

\
 
 \ /
  Last update: 2018-03-19 20:53    [W:0.213 / U:0.396 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site