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    Subject[PATCH 4.9 154/241] pwm: tegra: Increase precision in PWM rate calculation
    Date
    4.9-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Laxman Dewangan <ldewangan@nvidia.com>


    [ Upstream commit 250b76f43f57d578ebff5e7211eb2c73aa5cd6ca ]

    The rate of the PWM calculated as follows:

    hz = NSEC_PER_SEC / period_ns;
    rate = (rate + (hz / 2)) / hz;

    This has the precision loss in lower PWM rate.

    Change this to have more precision as:

    hz = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC * 100, period_ns);
    rate = DIV_ROUND_CLOSEST(rate * 100, hz)

    Example:

    1. period_ns = 16672000, PWM clock rate is 200 KHz.

    Based on old formula
    hz = NSEC_PER_SEC / period_ns
    = 1000000000ul/16672000
    = 59 (59.98)
    rate = (200K + 59/2)/59 = 3390

    Based on new method:
    hz = 5998
    rate = DIV_ROUND_CLOSE(200000*100, 5998) = 3334

    If we measure the PWM signal rate, we will get more accurate
    period with rate value of 3334 instead of 3390.

    2. period_ns = 16803898, PWM clock rate is 200 KHz.

    Based on old formula:
    hz = 59, rate = 3390

    Based on new formula:
    hz = 5951, rate = 3360

    The PWM signal rate of 3360 is more near to requested period
    than 3333.

    Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
    Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
    Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/pwm/pwm-tegra.c | 7 +++++--
    1 file changed, 5 insertions(+), 2 deletions(-)

    --- a/drivers/pwm/pwm-tegra.c
    +++ b/drivers/pwm/pwm-tegra.c
    @@ -76,6 +76,7 @@ static int tegra_pwm_config(struct pwm_c
    struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
    unsigned long long c = duty_ns;
    unsigned long rate, hz;
    + unsigned long long ns100 = NSEC_PER_SEC;
    u32 val = 0;
    int err;

    @@ -95,9 +96,11 @@ static int tegra_pwm_config(struct pwm_c
    * cycles at the PWM clock rate will take period_ns nanoseconds.
    */
    rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH;
    - hz = NSEC_PER_SEC / period_ns;

    - rate = (rate + (hz / 2)) / hz;
    + /* Consider precision in PWM_SCALE_WIDTH rate calculation */
    + ns100 *= 100;
    + hz = DIV_ROUND_CLOSEST_ULL(ns100, period_ns);
    + rate = DIV_ROUND_CLOSEST(rate * 100, hz);

    /*
    * Since the actual PWM divider is the register's frequency divider

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