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    SubjectRe: [PATCH v3 09/11] cpufreq: tegra124-cpufreq: extend to support Tegra210
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    On 13/03/18 09:51, Peter De Schrijver wrote:
    > On Mon, Mar 12, 2018 at 12:15:22PM +0000, Jon Hunter wrote:
    >>
    >> On 06/02/18 16:34, Peter De Schrijver wrote:
    >>> Tegra210 has a very similar CPU clocking scheme than Tegra124. So add
    >>> support in this driver. Also allow for the case where the CPU voltage is
    >>> controlled directly by the DFLL rather than by a separate regulator object.
    >>>
    >>> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
    >>> ---
    >>> drivers/cpufreq/tegra124-cpufreq.c | 15 ++++++++-------
    >>> 1 file changed, 8 insertions(+), 7 deletions(-)
    >>>
    >>> diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c
    >>> index 4353025..f8e01a8 100644
    >>> --- a/drivers/cpufreq/tegra124-cpufreq.c
    >>> +++ b/drivers/cpufreq/tegra124-cpufreq.c
    >>> @@ -64,7 +64,8 @@ static void tegra124_cpu_switch_to_pllx(struct tegra124_cpufreq_priv *priv)
    >>> {
    >>> clk_set_parent(priv->cpu_clk, priv->pllp_clk);
    >>> clk_disable_unprepare(priv->dfll_clk);
    >>> - regulator_sync_voltage(priv->vdd_cpu_reg);
    >>> + if (priv->vdd_cpu_reg)
    >>> + regulator_sync_voltage(priv->vdd_cpu_reg);
    >>> clk_set_parent(priv->cpu_clk, priv->pllx_clk);
    >>> }
    >>
    >> OK, so this bit does not make sense to me. In the above we are switching
    >> from the DFLL to the PLL (ie. disabling the DFLL) and so to ensure we
    >> are operating at the correct voltage after disabling the DFLL we need to
    >> sync the voltage. Seems we would need to do this for all devices, no?
    >> How is the different between Tegra124 and Tegra210?
    >
    > Yes. So in case of i2c the regulator framework will reapply the voltage it
    > knows which in our case is the boot voltage for VDD_CPU because noone else
    > from a regulator framework pov has ever changed the voltage. In case of PWM
    > putting the PWM output pad in tri state will cause the OVR regulator to output
    > a hardware defined voltage. This is done as part of the dfll_clk_disable()
    > function. To summarize:

    So this is the piece of information I was missing. Maybe add this to the
    changelog so it is clear why we do not need to handle the cpu rail in
    the case of PWM.

    Cheers
    Jon

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    nvpublic

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