Messages in this thread | | | From | Joel Stanley <> | Date | Tue, 13 Mar 2018 16:10:01 +1030 | Subject | Re: [PATCH v2 1/2] clk: aspeed: Fix is_enabled for certain clocks |
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On Fri, Mar 9, 2018 at 7:27 AM, Eddie James <eajames@linux.vnet.ibm.com> wrote: > Some of the Aspeed clocks are disabled by setting the relevant bit in > the "clock stop control" register to one, while others are disabled by > setting their bit to zero. The driver already uses a flag per gate to > identify this behavior, but doesn't apply it in the clock is_enabled > function. > > Use the existing gate flag to correctly return whether or not a clock > is enabled in the aspeed_clk_is_enabled function. > > Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com>
Fixes: 6671507f0fbd ("clk: aspeed: Handle inverse polarity of USB port 1 clock gate")
Reviewed-by: Joel Stanley <joel@jms.id.au>
Cheers,
Joel
> --- > drivers/clk/clk-aspeed.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c > index 9f7f931..1687771 100644 > --- a/drivers/clk/clk-aspeed.c > +++ b/drivers/clk/clk-aspeed.c > @@ -259,11 +259,12 @@ static int aspeed_clk_is_enabled(struct clk_hw *hw) > { > struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); > u32 clk = BIT(gate->clock_idx); > + u32 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk; > u32 reg; > > regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, ®); > > - return (reg & clk) ? 0 : 1; > + return ((reg & clk) == enval) ? 1 : 0; > } > > static const struct clk_ops aspeed_clk_gate_ops = { > -- > 1.8.3.1 >
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