Messages in this thread | | | From | Linus Torvalds <> | Date | Mon, 12 Mar 2018 10:12:38 -0700 | Subject | Re: [tip:x86/mm] x86/boot/compressed/64: Describe the logic behind the LA57 check |
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On Mon, Mar 12, 2018 at 10:06 AM, Andy Lutomirski <luto@kernel.org> wrote: > > I'd be surprised if there's a noticeable performance hit on anything > except the micro-est of benchmarks. We're talking one extra > intermediate paging structure cache entry in use, maybe a few data > cache lines, and (wild guess) 0 extra cycles on a TLB miss in the > normal case. This is because the walks are almost never going to > start at the root.
Probably. But VM people may disagree if they already have high TLB miss costs.
> The real hit will be the extra page table for every task.
.. and it's unclear how noticeable that might be. It's not like it's per-thread, only per process, and very few people have so many processes that a page per process matters.
But regardless, I think we're better off with a "wait and see" approach.
IOW, try to use 5-level whenever possible for now, and _if_ somebody actually can show that 4-level page tables perform better or have some other advantage, we can then try to be clever later when it's all tested and it's just an optimization, not a "that code won't even run normally and gets basically zero coverage".
Linus
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