Messages in this thread | | | Date | Fri, 09 Feb 2018 16:25:29 +0900 | From | Chanwoo Choi <> | Subject | Re: [PATCH 1/3] clk: exynos5433: Extend list of available AUD_PLL output frequencies |
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On 2018년 02월 07일 22:04, Sylwester Nawrocki wrote: > On 02/07/2018 12:24 PM, Chanwoo Choi wrote: >> Could you share your equation? >> because your result is a little bit different of my result. >> - my equation : ((mdiv + kdiv/65535) x 24MHz) / (pdiv x POWER(2,sdiv)) > > It resembles the code from samsung_pll36xx_recalc_rate(): > > (24 * 10^6 * (M * 2^16 + K)) / (P * 2^S) / 2^16 > > and a more accurate one > > ROUNDDOWN(ROUNDDOWN(24 * 10^6 * (M * 2^16 + K), 0) / ROUNDDOWN(P * 2^S, 0) / 2^16, 0) > > Shouldn't you substitute 65535 with 65536?
65536 is right. It is my mistake using 65535. Thanks for your share.
-- Best Regards, Chanwoo Choi Samsung Electronics
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