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    Subject[PATCH 3.16 102/254] MIPS: ptrace: Fix FP context restoration FCSR regression
    3.16.55-rc1 review patch.  If anyone has any objections, please let me know.

    ------------------

    From: "Maciej W. Rozycki" <macro@imgtec.com>

    commit 4249548454f7ba4581aeee26bd83f42b48a14d15 upstream.

    Fix a floating-point context restoration regression introduced with
    commit 9b26616c8d9d ("MIPS: Respect the ISA level in FCSR handling")
    that causes a Floating Point exception and consequently a kernel oops
    with hard float configurations when one or more FCSR Enable and their
    corresponding Cause bits are set both at a time via a ptrace(2) call.

    To do so reinstate Cause bit masking originally introduced with commit
    b1442d39fac2 ("MIPS: Prevent user from setting FCSR cause bits") to
    address this exact problem and then inadvertently removed from the
    PTRACE_SETFPREGS request with the commit referred above.

    Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
    Cc: linux-mips@linux-mips.org
    Patchwork: https://patchwork.linux-mips.org/patch/13238/
    Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
    Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
    ---
    arch/mips/kernel/ptrace.c | 1 +
    1 file changed, 1 insertion(+)

    --- a/arch/mips/kernel/ptrace.c
    +++ b/arch/mips/kernel/ptrace.c
    @@ -176,6 +176,7 @@ int ptrace_setfpregs(struct task_struct
    }

    __get_user(value, data + 64);
    + value &= ~FPU_CSR_ALL_X;
    fcr31 = child->thread.fpu.fcr31;
    mask = boot_cpu_data.fpu_msk31;
    child->thread.fpu.fcr31 = (value & ~mask) | (fcr31 & mask);
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