Messages in this thread | | | Subject | Re: [PATCH 2/2] drm/sun4i: Handle DRM_MODE_FLAG_**SYNC_POSITIVE correctly | From | Giulio Benetti <> | Date | Wed, 28 Feb 2018 16:56:56 +0100 |
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Hi,
Il 16/02/2018 16:50, Maxime Ripard ha scritto: > On Thu, Feb 15, 2018 at 07:05:56PM +0100, Giulio Benetti wrote: >>> If so, and if remember the captures properly, the sampling would occur >>> right before the rise, and not really around the fall. >>> >>> Would 2/3 be better here? >> >> Yes, you're right, 2/3 phase is better: >> >> 1/3 phase: https://pasteboard.co/H4VehON.png >> 2/3 phase: https://pasteboard.co/H4Veq8a.png >> >> Take a look at the bit in middle(yellow) sampled by clock(blue). >> >> Rising edge is almost in the middle of D0 bit. >> >>> >>>> According to scope captures above on both A20 and A33. >>>> Unfortunately I don't have other boards for the other SoCs to take captures. >>>> >>>> What do you think? >>> >>> I guess we can make that part applicable to all SoCs, we haven't seen >>> any significant differences on those part. >> >> So let's keep: >> - As normal(rising edge) => IO_POL_REG "0x2 => 2/3 phase" >> - As inverted(falling edge) => IO_POL_REG "0x0 => normal phase" > > I was actually thinking 1/3 for rising, 2/3 for falling.
1/3 is almost the same waveform as D0, having rising an falling edges almost in sync with D0. It's not so clear because DCLK has a bad figure, but it is that way.
2/3 instead is almost in the middle of D0 as rising.
Summarizing: - use 0/3 as falling, then DRM_BUS_FLAG_PIXDATA_NEGEDGE - use 2/3 as rising, then DRM_BUS_FLAG_PIXDATA_POSEDGE
I follow with a new patch using clk_set_phase function.
> > Maxime >
-- Giulio Benetti CTO
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