Messages in this thread | | | Date | Mon, 26 Feb 2018 20:55:05 +0100 (CET) | From | Thomas Gleixner <> | Subject | Re: [PATCH v3 2/4] x86/speculation: Support "Enhanced IBRS" on future CPUs |
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On Tue, 20 Feb 2018, David Woodhouse wrote: > On Tue, 2018-02-20 at 11:42 +0100, Thomas Gleixner wrote: > > > > > > However, Paolo is very insistent that taking the trap every time is > > > > actually a lot *slower* than really frobbing IBRS on certain > > > > microarchitectures, so my hand-waving "pfft, what did they expect?" is > > > > not acceptable. > > > > > > > > Which I think puts us back to the "throwing the toys out of the pram" > > > > There are no more toys in the pram. I threw them all out weeks ago ... > > One option is to take the patch as-is¹ with the trap on every access. > As soon as Intel define that 'IBRS_ALL_AND_THE_BIT_IS_A_NOOP' bit in > MSR_IA32_ARCH_CAPABILITIES, *then* we can expose it to guests directly > again just as we do at the moment.
Arjan, is there any update on this?
Thanks,
tglx | |