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    Subject[PATCH 3.16 179/328] x86/microcode: Update the new microcode revision unconditionally
    3.16.62-rc1 review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Filippo Sironi <sironi@amazon.de>

    commit 8da38ebaad23fe1b0c4a205438676f6356607cfc upstream.

    Handle the case where microcode gets loaded on the BSP's hyperthread
    sibling first and the boot_cpu_data's microcode revision doesn't get
    updated because of early exit due to the siblings sharing a microcode
    engine.

    For that, simply write the updated revision on all CPUs unconditionally.

    Signed-off-by: Filippo Sironi <sironi@amazon.de>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    Cc: prarit@redhat.com
    Link: http://lkml.kernel.org/r/1533050970-14385-1-git-send-email-sironi@amazon.de
    [bwh: Backported to 3.16:
    - Keep returning 0 on success
    - Adjust context]
    Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
    ---
    --- a/arch/x86/kernel/cpu/microcode/amd.c
    +++ b/arch/x86/kernel/cpu/microcode/amd.c
    @@ -214,26 +214,26 @@ int apply_microcode_amd(int cpu)
    rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);

    /* need to apply patch? */
    - if (rev >= mc_amd->hdr.patch_id) {
    - c->microcode = rev;
    - uci->cpu_sig.rev = rev;
    - return 0;
    - }
    + if (rev >= mc_amd->hdr.patch_id)
    + goto out;

    if (__apply_microcode_amd(mc_amd)) {
    pr_err("CPU%d: update failed for patch_level=0x%08x\n",
    cpu, mc_amd->hdr.patch_id);
    return -1;
    }
    - pr_info("CPU%d: new patch_level=0x%08x\n", cpu,
    - mc_amd->hdr.patch_id);

    - uci->cpu_sig.rev = mc_amd->hdr.patch_id;
    - c->microcode = mc_amd->hdr.patch_id;
    + rev = mc_amd->hdr.patch_id;
    +
    + pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev);
    +
    +out:
    + uci->cpu_sig.rev = rev;
    + c->microcode = rev;

    /* Update boot_cpu_data's revision too, if we're on the BSP: */
    if (c->cpu_index == boot_cpu_data.cpu_index)
    - boot_cpu_data.microcode = mc_amd->hdr.patch_id;
    + boot_cpu_data.microcode = rev;

    return 0;
    }
    --- a/arch/x86/kernel/cpu/microcode/intel.c
    +++ b/arch/x86/kernel/cpu/microcode/intel.c
    @@ -161,11 +161,8 @@ int apply_microcode(int cpu)
    * already.
    */
    rev = intel_get_microcode_revision();
    - if (rev >= mc_intel->hdr.rev) {
    - uci->cpu_sig.rev = rev;
    - c->microcode = rev;
    - return 0;
    - }
    + if (rev >= mc_intel->hdr.rev)
    + goto out;

    /* write microcode via MSR 0x79 */
    wrmsr(MSR_IA32_UCODE_WRITE,
    @@ -185,8 +182,9 @@ int apply_microcode(int cpu)
    mc_intel->hdr.date >> 24,
    (mc_intel->hdr.date >> 16) & 0xff);

    +out:
    uci->cpu_sig.rev = rev;
    - c->microcode = rev;
    + c->microcode = rev;

    /* Update boot_cpu_data's revision too, if we're on the BSP: */
    if (c->cpu_index == boot_cpu_data.cpu_index)
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