Messages in this thread Patch in this message | | | Date | Thu, 6 Dec 2018 09:58:27 +0000 | From | Will Deacon <> | Subject | Re: [PATCH v2 1/7] arm64: capabilities: Merge entries for ARM64_WORKAROUND_CLEAN_CACHE |
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On Wed, Dec 05, 2018 at 05:14:53PM +0000, Suzuki K Poulose wrote: > On 05/12/2018 15:02, Will Deacon wrote: > >On Fri, Nov 30, 2018 at 05:18:00PM +0000, Suzuki K Poulose wrote: > >>diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h > >>index 12f93e4d..2e26375 100644 > >>--- a/arch/arm64/include/asm/cputype.h > >>+++ b/arch/arm64/include/asm/cputype.h > >>@@ -151,6 +151,7 @@ struct midr_range { > >> .rv_max = MIDR_CPU_VAR_REV(v_max, r_max), \ > >> } > >>+#define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max) > > > >What's the point of this macro? > > That can be used to specify a set of MIDRs which has the same "variant" but a > range of "revisions". This is used for the A53 errata and also for the Cavium > errata in the following patch.
Gah, I read this at least 10 times and I /still/ failed to spot the extra 'v' argument to MIDR_RANGE!
Ignore my silly comment; I'll queue this up today. Thanks.
Will
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