Messages in this thread | | | From | Stephen Boyd <> | Subject | Re: [PATCH V6 4/9] clk: imx: add pfdv2 support | Date | Mon, 03 Dec 2018 11:31:54 -0800 |
| |
Quoting A.s. Dong (2018-11-14 05:01:47) > The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System > Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP. > > NOTE pfdv2 can only be operated when clk is gated. > > Cc: Stephen Boyd <sboyd@codeaurora.org> > Cc: Michael Turquette <mturquette@baylibre.com> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: Anson Huang <Anson.Huang@nxp.com> > Cc: Bai Ping <ping.bai@nxp.com> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> > > ---
Applied to clk-next
| |