Messages in this thread | | | Subject | Re: [PATCH v3 3/3] platform/x86: intel_pmc_core: Decode Snoop / Non Snoop LTR | From | "Bhardwaj, Rajneesh" <> | Date | Tue, 6 Nov 2018 02:30:41 +0530 |
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On 03-Nov-18 12:02 AM, Andy Shevchenko wrote: > On Fri, Nov 2, 2018 at 12:37 PM Rajneesh Bhardwaj > <rajneesh.bhardwaj@linux.intel.com> wrote: >> The LTR values follow PCIE LTR encoding format and can be decoded as per >> https://pcisig.com/sites/default/files/specification_documents/ECN_LatencyTolnReporting_14Aug08.pdf >> >> This adds support to translate the raw LTR values as read from the PMC >> to meaningful values in nanosecond units of time. >> +#include <linux/bits.h> > I told you something different, i.e. put this header where you _use_ > it, i.o.w into the header file.
Oops! Will move it to the header.
> >> +#define LTR_REQ_NONSNOOP BIT(31) >> +#define LTR_REQ_SNOOP BIT(15) >> +#define LTR_DECODED_VAL GENMASK(9, 0) >> +#define LTR_DECODED_SCALE GENMASK(12, 10) > If these are in one register, please keep ordered by start bit.
Sure, will do.
> > The rest is fine. >
Many thanks again for your detailed review.
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