Messages in this thread | | | Date | Mon, 5 Nov 2018 10:34:13 +0100 | From | Peter Zijlstra <> | Subject | Re: [PATCH v1 1/8] perf/x86: add support to mask counters from host |
| |
On Fri, Nov 02, 2018 at 05:08:31PM +0800, Wei Wang wrote: > On 11/01/2018 10:52 PM, Peter Zijlstra wrote: > > > @@ -723,6 +724,9 @@ static void perf_sched_init(struct perf_sched *sched, struct event_constraint ** > > > sched->max_weight = wmax; > > > sched->max_gp = gpmax; > > > sched->constraints = constraints; > > > +#ifdef CONFIG_CPU_SUP_INTEL > > > + sched->state.used[0] = cpuc->intel_ctrl_guest_mask; > > > +#endif > > NAK. This completely undermines the whole purpose of event scheduling. > > > > Hi Peter, > > Could you share more details how it would affect the host side event > scheduling?
Not all counters are equal; suppose you have one of those chips that can only do PEBS on counter 0, and then hand out 0 to the guest for some silly event. That means nobody can use PEBS anymore.
> Would you have any suggestions?
I would suggest not to use virt in the first place of course ;-)
But whatever you do; you have to keep using host events to emulate the guest PMU. That doesn't mean you can't improve things; that code is quite insane from what you told earlier.
| |