Messages in this thread | | | Date | Mon, 5 Nov 2018 09:41:54 +0100 | From | Maxime Ripard <> | Subject | Re: [PATCH 1/7] clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width |
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On Thu, Nov 01, 2018 at 12:06:28AM +0530, Jagan Teki wrote: > MUX bits for MMC clock register range are 25:24 where 24 is shift > and 2 is width So fix the width number from 3 to 2. > > Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU") > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Applied for 4.21, thanks! Maxime
-- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com [unhandled content-type:application/pgp-signature] | |