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    Subject[PATCH 4.19 290/361] iommu/arm-smmu: Ensure that page-table updates are visible before TLBI
    Date
    4.19-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Will Deacon <will.deacon@arm.com>

    commit 7d321bd3542500caf125249f44dc37cb4e738013 upstream.

    The IO-pgtable code relies on the driver TLB invalidation callbacks to
    ensure that all page-table updates are visible to the IOMMU page-table
    walker.

    In the case that the page-table walker is cache-coherent, we cannot rely
    on an implicit DSB from the DMA-mapping code, so we must ensure that we
    execute a DSB in our tlb_add_flush() callback prior to triggering the
    invalidation.

    Cc: <stable@vger.kernel.org>
    Cc: Robin Murphy <robin.murphy@arm.com>
    Fixes: 2df7a25ce4a7 ("iommu/arm-smmu: Clean up DMA API usage")
    Signed-off-by: Will Deacon <will.deacon@arm.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/iommu/arm-smmu.c | 6 ++++++
    1 file changed, 6 insertions(+)

    --- a/drivers/iommu/arm-smmu.c
    +++ b/drivers/iommu/arm-smmu.c
    @@ -469,6 +469,9 @@ static void arm_smmu_tlb_inv_range_nosyn
    bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
    void __iomem *reg = ARM_SMMU_CB(smmu_domain->smmu, cfg->cbndx);

    + if (smmu_domain->smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)
    + wmb();
    +
    if (stage1) {
    reg += leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA;

    @@ -510,6 +513,9 @@ static void arm_smmu_tlb_inv_vmid_nosync
    struct arm_smmu_domain *smmu_domain = cookie;
    void __iomem *base = ARM_SMMU_GR0(smmu_domain->smmu);

    + if (smmu_domain->smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)
    + wmb();
    +
    writel_relaxed(smmu_domain->cfg.vmid, base + ARM_SMMU_GR0_TLBIVMID);
    }


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