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    Subject[PATCH 2/4] MIPS: Correct `mmiowb' barrier for `wbflush' platforms
    Redefine `mmiowb' in terms of `iobarrier_w' so that it works correctly 
    for MIPS I platforms, which have no SYNC machine instruction and use a
    call to `wbflush' instead.

    This doesn't change the semantics for CONFIG_CPU_CAVIUM_OCTEON, because
    `iobarrier_w' expands to `wmb', which is ultimately the same as the
    current arrangement. For MIPS I platforms this not only makes any code
    that would happen to use `mmiowb' build and run, but it actually
    enforces the ordering required as well, as `iobarrier_w' has it already
    covered with the use of `wmb'.

    Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
    ---
    arch/mips/include/asm/io.h | 11 +++--------
    1 file changed, 3 insertions(+), 8 deletions(-)

    linux-mips-mmiowb.patch
    Index: linux-20180930-3maxp/arch/mips/include/asm/io.h
    ===================================================================
    --- linux-20180930-3maxp.orig/arch/mips/include/asm/io.h
    +++ linux-20180930-3maxp/arch/mips/include/asm/io.h
    @@ -91,6 +91,9 @@ static inline void set_io_port_base(unsi
    #define iobarrier_w() wmb()
    #define iobarrier_sync() iob()

    +/* Some callers use this older API instead. */
    +#define mmiowb() iobarrier_w()
    +
    /*
    * Thanks to James van Artsdalen for a better timing-fix than
    * the two short jumps: using outb's to a nonexistent port seems
    @@ -573,14 +576,6 @@ BUILDSTRING(l, u32)
    BUILDSTRING(q, u64)
    #endif

    -
    -#ifdef CONFIG_CPU_CAVIUM_OCTEON
    -#define mmiowb() wmb()
    -#else
    -/* Depends on MIPS II instruction set */
    -#define mmiowb() asm volatile ("sync" ::: "memory")
    -#endif
    -
    static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
    {
    memset((void __force *) addr, val, count);
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