Messages in this thread | | | Date | Thu, 4 Oct 2018 13:22:07 +0100 | From | Will Deacon <> | Subject | Re: [PATCH] arm_pmu: Delete incorrect cache event mapping for some armv8_pmuv3 events. |
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Hi Ganapat,
On Thu, Oct 04, 2018 at 11:12:09AM +0530, Ganapatrao Kulkarni wrote: > can you please pull this patch?
I still don't like the idea of just removing events like this, especially when other architectures (including some x86 and Power CPUs afaict) playa similar games for generic events, and these events do actually appear in user code.
I also don't understand why you remove the TLB events. I think that logic would imply we should remove all of the events, because we can't distinguish prefetches from reads either. If we want to be consistent, then I think we should just remove the OP_WRITE events for L1D and BPU -- would you be ok with that instead?
Also, looking at the code, I think our PMCEID parsing is broken for 8.1 parts, where the upper 32 bits of the register are offset by 0x4000 in the event numbering space.
Will
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