lkml.org 
[lkml]   [2018]   [Oct]   [26]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH v3 21/25] clk: sunxi-ng: a64: Add min and max rate for PLL_MIPI
    Date
    Manual noted to use PLL_MIPI rate 500MHz to 1.4GHz,
    but lowering the min rate by 300MHz can result proper
    working nkms divider with the help of desired dclock
    rate from panel driver.

    Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
    Acked-by: Stephen Boyd <sboyd@kernel.org>
    Tested-by: Jagan Teki <jagan@amarulasolutions.com>
    ---
    Changes for v3:
    - collect Stephen Ack
    - add tested credit
    Changes for v2:
    - none

    drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 ++
    1 file changed, 2 insertions(+)

    diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
    index 019d67bf97c4..5a3a5b821f8b 100644
    --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
    +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
    @@ -167,6 +167,8 @@ static struct ccu_nkm pll_mipi_clk = {
    .n = _SUNXI_CCU_MULT(8, 4),
    .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
    .m = _SUNXI_CCU_DIV(0, 4),
    + .min_rate = 300000000, /* Actual rate is 500MHz */
    + .max_rate = 1400000000UL,
    .common = {
    .reg = 0x040,
    .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",
    --
    2.18.0.321.gffc6fa0e3
    \
     
     \ /
      Last update: 2018-10-26 16:47    [W:3.941 / U:0.052 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site