lkml.org 
[lkml]   [2018]   [Oct]   [23]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH v2 12/15] clk: sunxi-ng: a64: Add min and max rate for PLL_MIPI
    Date
    A64 manual say PLL_MIPI rates are 500MHz to 1.4GHz, but
    using minimum 500MHz can't release the clock and which
    is not working.

    So use working minimum rate as 300MHz which is tested on
    Bananapi DSI panel.

    Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
    ---
    Changes for v2:
    - new patch

    drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 ++
    1 file changed, 2 insertions(+)

    diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
    index 019d67bf97c4..5a3a5b821f8b 100644
    --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
    +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
    @@ -167,6 +167,8 @@ static struct ccu_nkm pll_mipi_clk = {
    .n = _SUNXI_CCU_MULT(8, 4),
    .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
    .m = _SUNXI_CCU_DIV(0, 4),
    + .min_rate = 300000000, /* Actual rate is 500MHz */
    + .max_rate = 1400000000UL,
    .common = {
    .reg = 0x040,
    .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",
    --
    2.18.0.321.gffc6fa0e3
    \
     
     \ /
      Last update: 2018-10-23 17:52    [W:4.141 / U:0.048 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site